1. Field of the Invention
The present invention relates to a semiconductor device which can be integrated at a high density and a manufacturing method thereof.
2. Description of the Prior Art
As shown in FIG. 1(a), in a first prior art MOS type semiconductor device, a gate oxide film 922 and a gate electrode 923 are formed successively on a semiconductor substrate 921 of a conduction type, and a source region 924 and a drain region 925 are formed by implant impurity ions into the semiconductor substrate 921 with use of the gate electrode 923 as a mask. Then, as shown in FIG. 1(b), an insulating film 926 is formed on the whole surface, and openings 927, 928, 929 for contact are formed in the insulating film 926 and gate oxide film 922 selectively and metalization layers 930, 931, 932 are formed. On the other hand, in another prior art semiconductor device shown in FIG. 2, in order to decrease the capacitance due to a substrate, a p-type semiconductor film 912 is formed on an electrical insulator film 911. Then, an n-type source region 913 and an n-type drain region 914 are formed in the semiconductor film 912, and a gate oxide film 915 and a gate electrode 916 are formed successively on a channel region interposed between the two regions 913 and 914. An insulating film (not shown) is formed next on the whole surface, and openings (not shown) are formed in the insulating film for contact with the source and drain regions 913, 914 and with the gate electrode 916. Finally, metalization layers (not shown) for contact are formed to complete a semiconductor device.
In the prior art MOS semiconductor device structures, the gate oxide film 922, 915 the gate electrode 923, 916 and the metalization layers 930, 931, 932 are formed above the semiconductor substrate 921, 911. Therefore, the surface under the metalization layer is uneven largely and the metalization layer is liable to be broken. And, when it is demanded to decrease the pattern size, the thicknesses of the layers composing the device have to be decreased in order to prevent the breakage of line due to the large aspect ratio of a longitudinal length to a lateral length of the openings. Further, if the thicknesses of the gate electrode 923, 916 and of the metalization layers 930, 931, 932 are decreased, the resistances increase and the electrical characteristics become worse.
FIG. 3 shows a prior art complementary MOS (CMOS) device, which is manufactured as follows: In a semiconductor substrate 941 of a first conduction type for example p-type, a well layer 942 of a second conduction type different from the first one, that is n-type, is formed. Then, after a gate oxide film 943 is formed on the semiconductor substrate 941, a polycrystalline semiconductor film is formed on the gate oxide film 943, and gate electrodes 944a, 944b are formed from the polycrystalline semiconductor film with a photolithography process. Next, by using the gate electrode pattern 944a as a mask, impurity atoms of the second conduction type, n-type are diffused into the semiconductor substrate 941 to form source and drain areas 945 of the second conduction type. On the other hand, in the well layer 942 of the second conduction type, source and drain regions 946 of the first conduction type different from that of the well layer 942 are formed with use of the gate electrode 944b as a mask.
The obtained CMOS type semiconductor device comprises a transistor X of the second conduction type, including the source and drain regions 945 of the second conduction type, the gate oxide film 943 and the gate electrode 944a, and a transistor Y of the first conduction type, including the source and drain regions 946 of the first conduction type, the gate oxide film 943 and the gate electrode 944b.
Such a CMOS type device needs to provide a region for forming a transistor Y of a conduction type and another region for forming a transistor X of the other conduction type in the same plane of a semiconductor substrate. Therefore, it is hard to manufacture such a CMOS type device integrated at a higher density.